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Mrs. G. Soujanya (UG/PG FCD) is an Assistant Professor with 2.5 years teaching experience. Specializing in VLSI Design and skilled in Verilog, she has one international paper and guided 8 UG projects.
Date of Joining the Institution
16/07/2025
Teaching Experience
2.5 Years
Qualifications
UG
PG
PhD
Teaching Experience
Teaching Experience
2.5 Years
Industry Experience
Research Experience
Skills
Verilog, C
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PhD Guidance
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PhDs / Projects Guided
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